介绍了利用VHDL硬件描述语言结合FPGA可编程器件进行数字钟的设计，并通过数码管驱动电路动态显示计时结果。
The paper introduces the design of digital clock based on FPGA and VHDL, the time of clock can be displayed with the digital driving circuit.
随着PLD功能的日益强大，数字电路设计已经进入全面革新的时代，HDL语言正是这个时代有力的工具。
With the function of PLD becoming increasingly powerful, the innovation age of the digital circuit design has arrived, in which HDL language is a powerful tool.
对数据库中的数据研究和分析，利用统一建模语言(uml)分析和设计数字河道信息管理系统。
Through the research and analysis of data in the database, unified modeling language (UML) is used to analyze and design the digital river information management system.
莉萨·波洛克是该项目的高级设计师。她说这种把正文转成合成语言的新技术有助于解决数字信号的划分问。
Lisa Pollack is the project's senior producer. She said this new technology which turns text into synthesized speech, is helping to bridge the digital divide.
介绍了用8031单片机控制的电脑数字钟的硬件结构与软件设计，给出了汇编语言源程序。
This paper introduces hardware constitution and software design of digital clock controlled by 8031 single-chip microcomputer, and its assembly language program is given.
数字逻辑系统的设计离不开计算机辅助设计CAD工具的帮助，尤其是VHDL硬件描述语言。
Now, many digital logic systems cannot do without computer aided design CAD, especially the VHDL Hardware Description Language.
我的毕业设计的核心任务是：采用FPGA来制作一个基于VHDL语言编写的数字电压表。
I graduated from the core task is to design: FPGA to create a VHDL-based language of the digital voltmeter.
VHDL语言能方便地进行数字系统描述，而且能使逻辑综合产生更大的设计密度。
VHDL, however, can make effective description of the digital system and enable logical synthesis to produce high design density.
PMIC的设计目的是获取模拟图表和数字硬件描述语言。
The PMIC design intent is captured as analog schematics and digital HDL.
介绍多媒体公共广播系统的组成及CPLD(可编程逻辑器件)在数字系统设计中的应用，用AHDL语言描述程序设计。
This paper introduces the structure of a multimedia public broadcast system and the application of CPLD in designing a digital system, and gives a description of the program design in AHDL.
针对在VHDL语言课程教学中，如何设置数字电路设计中的数据对象的若干教学问题进行了探讨。
This paper gives some discussion about teaching experience in setting data objects in digital circuit designing during teaching VHDL project.
AHDL语言由于其易学易用的特点，适合数字电路工程设计，这样可以大大节省时间和人力物力。
Because of its qualities of easy learning and use, AHDL is appropriate to the design of digital circuit engineering, so a lot of time and manpower can be saved.
在设计上，建筑师运用了数字化建造方式的语言重新阐释了中国传统建筑的形式。
It is an interpretation of traditional Chinese architecture through the language of digital fabrication methods.
本文介绍在设计HJD-500/1000型数字交换机软件系统时在单板机环境下使用C语言的实现技术。
We'll introduce the technology of designing the software system of the HJD-500/1000 digital exchange using programming language C on TP-86D single-board computer.
利用先进的EDA工具，基于硬件描述语言，借助CPLD（复杂的可编程逻辑器件），可以进行系统级数字逻辑电路的设计。
We can design all kinds of digital logical circuits with advanced EDA tools and based on VHDL and CPLD.
一个镶嵌设计和难以捉摸的数字组合是保证，以确保你是无法用语言感兴趣。
A mix of tessellating design and an elusive figure is guaranteed to ensure that you are intrigued beyond words.
通过设计实例，介绍了利用VHDL语言进行数字系统设计的方法。
Through design examples, this paper introduces the method of digital systems design based on VHDL.
硬件描述语言(VHDL)是数字系统高层设计的核心，是实现数字系统设计新方法的关键技术之一。
VHDL is considered as a core of digital system design and a key technique of implement digital systems design.
很多公司抱怨他们没有足够的模拟设计人员，但数字人员和模拟人员没有共同语言和共同的工具。
A lot of companies complain they don't have enough analog designers, but the digital people and the analog people don't speak the same language and they don't have the same tools.
为此，我们选用了VRML作为实现三维数字城市的语言，并基于VRML相关技术实现了帮助用户参与三维数字城市设计的工具。
For that, we use VRML to construct the 3d virtual space and provide some tools for users to participate the design process.
为此，我们选用了VRML作为实现三维数字城市的语言，并基于VRML相关技术实现了帮助用户参与三维数字城市设计的工具。
For that, we use VRML to construct the 3d virtual space and provide some tools for users to participate the design process.
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