本文将从算法级并行处理、指令级并行处理与进程级并行处理等三个方面讨论嵌入式RISC体系结构的设计问题。
The design problem of an embedded RISC architecture in parallel processing of algorithm level, instruction level and process level is discussed in this paper.
多年来，处理器制造厂商在不断提高时钟速度和指令级并行性，因此单线程代码不需要修改就可在新的处理器上更快运行。
For years, processor makers consistently delivered increases in clock rates and instruction-level parallelism, so that single-threaded code executed faster on newer processors with no modification.
讨论了指令级并行运算环境中多媒体数据处理的实现方法和性能。
This paper presents the implementation approach and the experimental results of multimedia realtime processing on the ILP (Instruction Level Parallelism) computing platform.
新一代面向密集计算的高性能处理器普遍采用分布式寄存器文件来支撑ALU阵列，并通过VLIW开发指令级并行。
Newly-emerging high performance processors for intensive computing generally use distributed register files to support ALU array and to explore instruction level parallelism(ILP) by VLIW.
本课程的另外一个重点是运用在高性能处理器中的指令级并行的技术。
Another focus is on technologies to exploit instruction level parallelism in high-performance processors.
本课程的另外一个重点是运用在高性能处理器中的指令级并行的技术。
Another focus is on technologies to exploit instruction level parallelism in high-performance processors.
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