介绍一种可用于语音处理的低功耗、高速率的抽取和内插数字滤波器的集成电路设计方法。
A low power, high speed design method of decimation and interpolation digital filters for audio signal processing is described.
重点讨论了多级抽取和内插滤波器的设计，绘制了大量的图表使它们的设计简单明了且接近最优。
Emphasized on the design of multilevel decimation and multilevel interpolation, devised many schematics to simplify the design and made the design approaching optimization.
重点讨论了多级抽取和内插滤波器的设计，绘制了大量的图表使它们的设计简单明了且接近最优。
Emphasized on the design of multilevel decimation and multilevel interpolation, devised many schematics to simplify the design and made the design approaching optimization.
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