该电路建立在一个简单的异或非逻辑门和延迟线的基础上，通过抽样调查异或非门的输出来检测电路的错误点，引入的多余面积很少。
The circuit is based on a simple XNOR logic gate and delay lines to sample the output of the XNOR gate, so very little area is introduced.
该电路建立在一个简单的异或非逻辑门和延迟线的基础上，通过抽样调查异或非门的输出来检测电路的错误点，引入的多余面积很少。
The circuit is based on a simple XNOR logic gate and delay lines to sample the output of the XNOR gate, so very little area is introduced.
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