图5图示说明依照本发明的另一实施例具有两个交替延迟路径的脉冲宽度发生器的示例。
FIG. 5 illustrates an example of a pulse width generator with two alternate delay paths, according to another embodiment of the present invention.
依照本发明进一步的实施例，脉冲宽度发生器404可具有3,4,5,6或更多个分离的延迟路径。
According to further embodiments of the present invention, pulse width generator 404 can have 3, 4, 5, 6, or more separate delay paths.
脉冲宽度发生器404提供给信号VIN的延迟响应来自二极管405的信号和选择信号的变化而改变。
The delay that pulse width generator 404 provides to signal VIN varies in response to variations in the signal from diode 405 and the select signal.
脉冲宽度发生器404可包括例如一个或更多个延迟电路。
Pulse width generator 404 can include, for example, one or more delay circuits.
在VIN下降沿后的延迟时间周期中，脉冲宽度发生器404产生VOUT的下降沿。
Pulse width generator 404 generates a falling edge in VOUT a delayed period of time after the falling edge in VIN.
因此，脉冲宽度发生器404在VIN下降沿和随后的VOUT下降沿之间产生延迟。
Thus, pulse width generator 404 generates a delay between a falling edge of VIN and a subsequent falling edge of VOUT.
CADLL估计多径延迟和振幅，并进一步转化为对GNSS天线相位中心反射发生器的距离。
CADLL estimates the delays and amplitudes of multipath, which are further translated into the distances of the reflector generator with respect to the center of phase of the GNSS antenna.
CADLL估计多径延迟和振幅，并进一步转化为对GNSS天线相位中心反射发生器的距离。
CADLL estimates the delays and amplitudes of multipath, which are further translated into the distances of the reflector generator with respect to the center of phase of the GNSS antenna.
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