提出了可描述TSDC中寄生电流的方程。
An equation to describe the parasitic galvanic current in experimental TSDC is proposed.
热刺激电流测试中寄生电流的存在对测试结果会产生一定的影响。
Thermally stimulated current is used to obtain the parameters of dielectrics, but the parasitic galvanic current existing in test influences the consequence.
热刺激电流测试(TSC)中寄生电流的存在对测试结果会产生一定的影响。
Thermally stimulated current (TSC) is used to obtain the parameters of dielectrics, but the parasitic galvanic current existing in test influences the consequence.
热刺激电流测试(TSC)中寄生电流的存在对测试结果会产生一定的影响。
In this paper, the mechanism of TSC and parasitic conduction current is discussed.
泄漏电流是由测量电路和附近的电压源之间的寄生电阻通路产生的。
Leakage currents are generated by stray resistance paths between the measurement circuit and nearby voltage sources.
该模型的要点是表示技术指标如何迅速下降的。当越来越多的通道被连接在一起时，漏泄通路、寄生电容和误差电流都将会增加。
The main point of this model is to show how quickly specifications can degrade. As more channels are connected together, leakage paths, stray capacitances, and error currents all increase.
如果这时的电流比要测量的电流大得多，那么系统中一定存在着寄生泄漏通路，必须将其纠正。
If there is significant current compared to the current to be measured, there must be a stray leakage path, which should be corrected.
切换和测量具有高内阻的电压源会受各种误差的影响，包括偏移电流、寄生漏泄通路，以及静电干扰。
Switching and measuring voltage sources with high internal impedance are subject to a number of errors, including offset currents, stray leakage paths, and electrostatic interference.
由寄生电容引起的泄放电流在开通时产生很高的电流尖刺。
The discharge of circuits' parasitic capacitances leads to a high current spike during turning on.
本文从包括埋层影响的集区杂质分布出发，求出了寄生PNP晶体管的共基极电流放大系数。
We try to obtain the common-base current gain a of the parasitic PNP transistor from the eloping profile of the collector region including the effect of buried-layer.
阻尼电阻r 6：对火花放电电流起缓冲作用，并阻尼高压输出回路中lc分布参数引起的寄生振荡。
Buffer resistance R6: playing buffer effect on spark discharge current and hindering. The parasitic vibration brought by LC distributing parameters of high-voltage output loop.
由于以分 立的形式连接主电流通路和栅极驱动通路，因此可以减小寄生电感的影响，并提高电压变换效率。
Owing to the connection of the main current path and the gate driving path in discrete form, the influence of parasitic inductance can be reduced and voltage conversion efficiency can be improved.
设计中考虑到电流密度问题，寄生问题，对称性问题，天线效应以及ESD保护等。
Considering the issues such as current density, parasitic, symmetry, antenna effect and ESD.
对寄生的漏源串联电阻及其温度特性进行了详细探讨，计算结果表明，漏源串联电阻给漏源电流造成的衰减在温度升高后变得很大。
The result of calculation indicated that the attenuation of source-drain current caused by the source-drain resistance increased when temperature increased.
降低寄生源漏电阻可以获得更高的饱和电流、跨导和截至频率。
The calculated results also indicate that higher saturation current, transconductance, and cutoff frequency can be achieved by lowering the parasitic resistances.
电路板介电性能的缺陷会给寄生漏电流提供路径。
Imperfections in the board's dielectric properties can provide parasitic-leakage-current paths.
电路板介电性能的缺陷会给寄生漏电流提供路径。
Imperfections in the board's dielectric properties can provide parasitic-leakage-current paths.
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