这种结构由四部分构成：输入延迟单元、寄存器单元、滤波器单元和控制单元。
It comprises of four basic unit: input delay, filter, register bank, and control unit.
对实时红外atr系统的FPGA逻辑结构进行了研究，提出了一种以寄存器单元为控制核心的FPGA逻辑结构。
A logic structure of FPGA with registers unit as control kernel is proposed after studying the logic structure of FPGA of real time IR ATR system.
数字信号处理器包含了中央算术逻辑单元、乘法器单元、移位器单元、排序器单元、辅助寄存器单元、中断单元的设计。
The digit signal processor embodies the center arithmetic logic unit, Multiplier unit, Shifter unit, Sequencing unit, Auxiliary register unit, interception unit.
这些单元与基准时间寄存器相同，并且两个线程的PURR值的总和等于基准时间寄存器的值。
The units are the same as the time base register and the sum of the PURR values for both threads is equal to time base register.
其中没有标量(单元素)寄存器或操作。
There are no scalar (single-element) registers or operations.
在向量处理器上，寄存器可以作为一个单元进行处理，也可以作为多个单元进行处理。
On vector processors a register is treated both as a single unit and as multiple units.
从存储单元或寄存器快速地存取信息的能力。
A capability of accessing information quickly from storage unit or register.
除了ADDRESS - OF和LINAGE - COUNTER专用寄存器外，其他专用寄存器都可以从运行单元中引用。
Except for the ADDRESS-OF and LINAGE-COUNTER special registers, these special registers can be referenced from run unit.
在分析全扫描内建自测试(BIST)过高测试功耗原因的基础上，提出了一种选择部分寄存器成为扫描单元的部分扫描算法来实现低功耗BIST。
Based on the analysis of excessive power dissipation off ull-scan BIST, we present partial scan algorithm which selects a portion of registers for scan cells to implement low power BIST.
在电流工作方式下，通过设计优化的存储单元、新型高速电流灵敏放大器以及一种灵敏放大器控制信号产生电路，提高了寄存器堆的读取速度。
High speed is achieved by using current mode techniques, which include designing optimum register cell, new high speed current sense amplifier and sense amplifier control signal generator.
文章详细讨论了RTCC、OPTION寄存器、预定标器及同步延时单元的电路结构、工作原理及设计特点。
The paper details the RTCC, OPTION register, prescaler and sync delay circuit principle and design feature.
算法的硬件结构由模乘控制器、模幂控制器、数据寄存器和模乘运算单元构成。
The hardware architecture is made up of modular controller, modular exponentiation controller, data register, and modular multiplication operation units.
只需重编位，而不需额外寄存器或逻辑单元。
You do only a rewiring requiring no extra registers or logic.
论文分析了处理器内部部件的工作原理，详细阐述了微处理器的取指单元、译码单元、执行单元、寄存器组和控制核心的设计。
The work principle of every part of microprocessor is analyzed, and a strong emphasis is laid on the design of program counter, instructions decipher, execute unit, register group and control center.
寄存器是处理器内部的存储单元。
提出了一种高速低功耗脉冲寄存器的设计方法，并将其应用在高速DSP地址生成单元的设计中。
This paper proposes a high speed and low power pulse latch design, and integrates it to high speed DSP address generator.
在各单元中包括寄存器，各寄存器与时钟脉冲同步，依次取得逻辑运算结果并加以保存。
Each cell contains a register. Each register successively acquires logic calculation results in synchronization with a clock and maintains them.
中断处理器读寄存器，并提供信息，指出哪一个存储单元出现了奇偶错误。
An interrupt handler reads the register and provides messages indicating which memory bank caused the parity error.
第四章在FPGA平台上实现载波同步单元电路，并给出了实现后的FPGA资源消耗、寄存器传输逻辑(rtl)原理图。
In chapter 4, the circuit of the carrier synchronization unit is implemented on FPGA, the Resistor Transistor Logic (RTL) schemes are presented.
一种图形处理单元流水线，通过传送来自第一模块的围篱指令至寻址同步寄存器对而执行同步。
A GPU pipeline is synchronized by sending a fence command from a first module to an addressed synchronization register pair.
一种图形处理单元流水线，通过传送来自第一模块的围篱指令至寻址同步寄存器对而执行同步。
A GPU pipeline is synchronized by sending a fence command from a first module to an addressed synchronization register pair.
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