本发明公开了固态存储器装置中的数据恢复。
Embodiments herein provide data recovery techniques and configurations for solid state memory devices.
图14描绘施加于循环存储器装置的编程脉冲。
FIG. 14 depicts programming pulses applied to a cycled memory device.
用于控制快闪存储器装置的命令数据输入到控制器218。
Command data for controlling the flash memory device is input to the controller 218.
在其它设计中，存储器装置的其它部分(例如状态机)可计算ecc。
In other designs, other parts of the memory device, such as the state machine, can calculate the ECC.
该系统包括：内容分类单元，根据预定的准则分类该存储器装置的记录内容；
The system comprises: a content classification unit classifying the record contents of the memory in accordance with a predetermined rule;
设备的一些实施例涉及采用高密度类NOR存储器装置的类NAND存储器阵列。
Some embodiments of the apparatus relate to NAND-like memory arrays employing high- density NOR-like memory devices.
存储器装置包含多个存储于不同项目地址的服务例程，每个服务例程关联一个中断请求。
The memory device comprises a plurality of service routines stored at different entry addresses, each related to an interruption request.
这种快闪存储器装置有时称为二元快闪存储器装置，因为每个存储器元件可存储一个数据位。
Such a flash memory device is sometimes referred to as a binary flash memory device because each memory element can store one bit of data.
当将从所述存储器装置(100)读取数据时，可对所述经穿孔数据进行解码(120、122)。
The punctured data can be decoded (120, 122) when data is to be read from the memory device (100).
此外，如果输出数据的初始值有错误时，存储器装置亦可将错误的输出数据修正为正确的输出数据。
In addition, when an initial value of the output data has an error, the memory device can correct the wrong output data into correct output data.
包含本发明的感测放大器以及只读存储器的存储器装置可降低噪声干扰对只读存储器的输出数据的影响。
The memory device comprising the sensing amplifier and the ROM can reduce the influence of noise interference on the output data of the ROM.
所述存储器装置包括M个正规字线驱动器、虚设字线驱动器、存储器阵列、N个读出放大器和时序控制电路。
The memory device includes M normal word line drivers, a dummy word line driver, a memory array, N sense amplifiers, and a timing control circuit.
特定来说，在非易失性存储器装置经历许多编程循环时，电荷变为俘获在浮动栅极与沟道区之间的绝缘体或电介质中。
In particular, as a non-volatile memory device undergoes many programming cycles, charge becomes trapped in the insulator or dielectric between the floating gate and the channel region.
在用于对读取周期中读取位线上的剩余电荷放电的半导体存储器装置中，位线在除读取操作期间以外的全部时间均处于复位状态。
In a semiconductor memory device operative to discharge residual charge in a read bit line in a read cycle, the bit line is in the reset state at all times except during read operation.
本发明揭示根据例如速率兼容卷积码(RPCC)等速率兼容码将数据存储于非易失性固态存储器装置(100)中的设备及方法。
Apparatus and methods store data in a non-volatile solid state memory device (100) according to a rate-compatible code, such as a rate-compatible convolutional code (RPCC).
在一些实施例中，存储器装置包括用于提供读数据位的存储器阵列和用于生成与读数据位对应的CRC位的循环冗余码(CRC)生成器。
In some embodiments, a memory device includes a memory array to provide read data bits and a cyclic redundancy code (CRC) generator to generate CRC bits corresponding to the read data bits.
包含在ECM内的是一个可动的校正装置，或是可编程序的读存储器。
Contained within the ECM is a removable calibration unit, on programmable read - only memory.
半导体存储器已变得愈加普遍用于各种电子装置中。
Semiconductor memory has become increasingly popular for use in various electronic devices.
一个直接的存储器位址(DMA)通常被用在装置之间直接地传递信息，省略处理器。
A direct memory address (DMA) is normally used to transfer information directly between devices, bypassing the CPU.
录制结束后，取下存储器，把数字影像资料转入电脑或其他数字装置。
When finished recording, remove memory card and transfer digital videos to your computer or other digital device.
所述第一电路板包括存储器和用于控制所述装置的至少一种功能的控制电路。
The first circuit board includes a memory, and control circuitry for controlling at least one function of the apparatus.
含ecm动校正装置，编程序读存储器。
ECM is a removable calibration unit, on programmable read-only memory.
该装置还包括适于存储多个存储的分析物浓度的存储器。
The device further comprises a memory adapted to store a plurality of stored analyte concentrations.
ECC控制器将数据发送给用于将数 据传送到主机装置的直接存储器存取（DMA）缓冲器以及用于对数据进行错误 检测和纠错的ECC块。
The ECC controller transmits the data to a direct memory access (DMA) buffer for transfer to the host device, and to an ECC block for error detection and correction of the data.
该方法还包括将参考图像存储至与所述装置相关联的存储器中。
The method also includes storing the reference image in a memory associated with the device.
本发明公开了一种基于扫描链的存储器测试装置及其使用方法。
The invention discloses a memorizer test device based on a scan chain and a use method thereof.
本发明提供一种规划一存储器的方法、装置、系统及信息结构。
The present invention provides a method for planning a memory, its device, system and information structure.
本发明的具有薄形片的携带型存储器相关装置构造新颖，外形更具趣味性，能用于产业上。
The portable memory relative device with the slice has novel construction and interesting appearance and can be used in industries.
本发明还提供了一种获取非挥发存储器中失效二进制位地址分布信息的装置。
The invention further provides a device for obtaining the address distribution information of failure bits in non-volatile memory.
本发明提供的方法及装置防止具有分块存储功能或分区存储功能的存储器读损。
The inventive method and data can prevent memory read damage with segment memory function or region memory function.
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