存储单元和数据线用复位信号来控制，以使数据可在该半导体器件中被可靠地输出。

A memory cell and a data line are controlled with a reset signal, so that data can be reliably outputted in the semiconductor device.

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一个有趣的组合是来自莱迪思半导体公司，其ISPPAC - POWR607 - 01sn32 I电源监控器，看门狗和复位发生器(图4)。

An interesting combo comes from Lattice Semiconductor, with its ISPPAC-POWR607-01SN32I power supply supervisor, watchdog, and reset generator (Figure 4).

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在用于对读取周期中读取位线上的剩余电荷放电的半导体存储器装置中，位线在除读取操作期间以外的全部时间均处于复位状态。

In a semiconductor memory device operative to discharge residual charge in a read bit line in a read cycle, the bit line is in the reset state at all times except during read operation.

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在用于对读取周期中读取位线上的剩余电荷放电的半导体存储器装置中，位线在除读取操作期间以外的全部时间均处于复位状态。

In a semiconductor memory device operative to discharge residual charge in a read bit line in a read cycle, the bit line is in the reset state at all times except during read operation.

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