本文介绍一种实用的全数字锁相环方案。
This paper introduces a practic design version of all-digital PLL.
提出了一种具有自动变模控制的快速全数字锁相环。
A fast all digital phase-locked loop with automatic modulus control is presented.
对如何提高嵌入式全数字锁相环的锁定速度进行了研究。
How to raise the phase lock speed of embedded DPLL is researched.
提出了一种低功耗、快速锁定全数字锁相环的设计方法。
A design method for all DPLLs that with low power cost and high phase locked velocity has been proposed.
本文讨论的全数字锁相环包括过零检测器和环路滤波器。
This paper discusses an all digital phase-locked loop with a zero-crossing detector and a loop filter.
本文主要研究了基于全数字锁相环的谐振型逆变器频率跟踪的数字化控制方案。
The paper studies digital control scheme of resonance inverter frequency-tracking based on all digital phase-locked loop.
重点研究了基于FPGA的全数字锁相环频率跟踪技术和数字化SPWM实现技术。
All digital Phase-Locked Loop frequency tracking and digital SPWM realization technology based on FPGA are emphasized in the research.
作为全数字锁相环的关键模块，时间数字转换器的性能在一定程度决定其性能的好坏。
As the core module of all-digital PLL, time-to-digital converter determines its performance largely.
本文根据突发式数字通信快速锁相要求，提出一种位同步信号提取的新的快速全数字锁相环方案。
This paper presents a new type of all digital phase-locked loop(ADPLL)used for extracting a bit-synchronous signal to meet the requirements of the fast phase-locked in burst digital communication.
应用MATLAB分析了影响锁相环快速锁定的主要因素，提出了一种具有高精度自动变模控制的快速全数字锁相环。
The primary factor affecting fast phase lock is analyzed by using MATLAB. Then a fast all digital phase locked loop with a high precision automatic modulus control is proposed.
本文正是为数字化测速测距接收机设计并实现全数字化超窄带锁相环。
The digital very narrow-bandwidth Phase-Locked Loop(PLL) is designed and realized for the digital range and velocity measurement receiver.
本文正是为数字化测速测距接收机设计并实现全数字化超窄带锁相环。
The digital very narrow-bandwidth Phase-Locked Loop(PLL) is designed and realized for the digital range and velocity measurement receiver.
应用推荐