用于服务器，存储器和存储系统中的铅，用于交换，信号和传输，以及电信网络管理的网络基础设施设备中焊料中的铅。
Lead in solders for servers, storage and storage array systems, network infrastructure equipment for switching, signalling, transmission as well as network management for telecommunication.
依照图5中一个实施例，电路515是存储选择信号的静止状态的存储器电路。
According to one embodiment of FIG. 5, circuit 515 is a memory circuit that stores a static state for the select signal.
例如，存储器电路515可在现场可编程门阵列中存储配置位，其中一个配置位用于生成选择信号。
For example, memory circuit 515 can store configuration bits in a field programmable gate array, where one of the configuration bits is used to generate the select signal.
选择信号的状态可通过在存储器中存储选择信号的新值而改变。
The state of the select signal can be changed by storing a new value for the select signal in memory.
在采满一定的数据量后FIFO存储器发出半满信号，计算机从FIFO存储器中读出数据并进行数据处理，输出处理结果。
After the FIFO is half full, the computer read the data from the FIFO, then the data will be processed, and the testing result will be given out.
方法：利用大容量非易失性可电擦除的存储器存储生理信号的数字信息。
Methods: Making use of large capacity and non - volatile memory store digital information about physiologic signal.
数字射频存储器(DRFM)是一种微波信号存储部件。
Digital Radio Frequency Memory (DRFM) is a kind of microwave signal storage device.
文章介绍利用多时钟产生存储器接口控制信号的方法，为建立软核仿真平台提供了一个新的途径。
This paper presents a way to generate control signals of the interface of memory using many clocks, and offers a new way for setting up the soft-core simulation platform.
其硬件部分主要由六个模块组成：信号调理模块、时间校对模块、存储器模块、网络控制模块、WDT模块和电源管理模块。
The hardware mainly comprises six modules: signal procession module, time adjusting module, memorizer module, network control module, WDT module and power management module.
数字射频存储器(DRFM)可以对雷达信号进行长时间的相干存储，为干扰现代相干体制雷达提供了有力的技术手段。
Digital Radio Frequency Memory (DRFM) can store radar signal coherently for a long time, it provides powerful means to counter new radar systems.
以单片机为核心的各传感器接口模块并行处理各传感器信号，并通过双口存储器与上位处理器通信。
Modules with microcontrollers in the system process their signals parallelly, and communicate with host processor by dual port memory.
并通过CPU和刷新地址电路共享存储器的方法，对系统输出的校验信号的波形进行编程。
Hz. The waveform of the correcting signal outputted from the system is coded with CPU and address modification circuits sharing the same memory.
系统由8051单片机、16位模数转换器MAX1177、存储器、信号调理电路和串口电路等构成。
The system is composed of 8051MCU, 16bits A/D MAX1177, memory, signal condition circuit and serial interface.
数字信号处理(dsp)具有并行的硬件乘法器、流水线结构以及快速的片内存储器等资源，其技术广泛地应用于数字信号处理的各个领域。
DSP technologies have applied in every field of digital signal processing because of its parallel multiplier, pipeline structure and fast On-Chip memory.
基于DSP的全数字化无刷直流电机伺服系统，由包括DSP和片外存储器的以TMS320F240组成的小系统，及反馈信号采集模块2部分组成。
The servo system for full-digital BLDC motor consists of DSP, memory subsystem based on TMS320F240 and the module for feedback signal acquisition.
分析了ADC转换器单端模式下对电压信号的采集过程和DMA控制器对外部存储器写入数据的过程。
The process of data acquisition with ADC controller in single-ended mode and the process of data storage with DMA controller are described.
所述读出放大器基于所述启用信号检测用于所述列存储器单元的位线。
The sense amplifiers detect bit lines for the columns of memory cells based on the enable signals.
从某种意义上说放大器控制信号产生的半导体存储器设备电路提供。
A sense amplifier control signal generating circuit of a semiconductor memory apparatus is provided.
便携电话机(1)的分组数据存储部(12)在分组数据比分组呼叫确立应答信号先被接收到的情况下，将分组数据存储到存储器。
If the packet data is received earlier than the packet call establishment response signal, a packet data storing part (12) of the mobile telephone unit (1) stores the packet data into a memory.
该系统采用了实时自适应ecg数据压缩算法(MFAN)、最优编码和大容量动态存储器等技术，可存储长达24小时的心电信号。
It can record and monitor ECG signal continuously up to 24 hours a real-time ECG compression algorithm (MFAN), DRAM technique and optimal coding method are presented.
泰瑞达是引领全球逻辑、RF、模拟、电源、混合信号、存储器技术的自动测试设备供应商。
Teradyne is a leading worldwide supplier of automatic test equipment for logic, RF, analog, power, mixed-signal, and memory technologies.
系统选w 78le516单片机和CPLD来构造控制电路，用读写速度快、功耗低的低电压外部数据存储器CF卡存储采集完的信号。
The system select W78LE516 MCU and CPLD to construct the control circuit and use quickly read and write low power consumption, low-voltage external data memory CF card to save the signal.
采用半导体存储器延迟信号，短时间平均器与长时间平均器对输入信号积分。
A semiconductor memory is used as a delay unit. Short-term averager and long-term averager integrate the input signals.
介绍了该操作系统的内核、存储器管理和分区、分配策略、多任务调度及任务间通过信号量和消息处理进行通信的机制、中断管理等。
Introduce the kernel, memory management and partition, allocation strategy, multi-task scheduling and how to communicate by semaphore and message handling as well as interrupt management.
之后在接收到分组呼叫确立应答信号的情况下，分组数据存储部(12)从存储器读出分组数据并从存储器删除。
Thereafter, when the packet call establishment response signal is received, the packet data storing part (12) reads the packet data from the memory and deletes it therefrom.
该只读存储器有效增加电荷陷阱，提高电路设计和信号处理的灵活性。
The read-only memory can efficiently increase charge traps, improve the flexibility of circuit design and signal processing.
它从存储器中取指令，提供存储器需要的地址和控制信号。
It fetches instructions from memory, supplying the address and control signals needed by memory to access its data.
但是，根据数字信号应用的特点，可以采用循环缓冲来减小指令存储器的功耗。
According to the characteristics of digital processing applications, loop buffering can be used to reduce the power consumption of instruction memories while fetching instructions.
基于单片机at89c51的数据采集子系统完成对多路声信号的同步采集，并把数字信号保存到片外共享存储器中。
The data acquisition subsystem based on AT89C51 acquires multichannel acoustic signal synchronistically and stores digital signals in the Shared memory.
基于单片机at89c51的数据采集子系统完成对多路声信号的同步采集，并把数字信号保存到片外共享存储器中。
The data acquisition subsystem based on AT89C51 acquires multichannel acoustic signal synchronistically and stores digital signals in the Shared memory.
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