本文介绍了一种使用非最长周期序列的非定长线性反馈移位寄存器作为数字系统内部测试生成器的方案，并给出了设计这种测试生成器的设计过程和算法。
In this paper, a scheme is presented, in which an infinite length's LFSR with non maximum cycle sequence is used as a built-in test generator in digital systems.
对于所有的实验电路，通过使用级数为确定性测试向量的确定位数量最大值的线性反馈移位寄存器，本策略可以编码所有的确定性测试向量。
For all benchmark circuits, the method is able to encode all deterministic test patterns using an LFSR whose size is equal to the maximum number of care bits in a test pattern.
对于所有的实验电路，通过使用级数为确定性测试向量的确定位数量最大值的线性反馈移位寄存器，本策略可以编码所有的确定性测试向量。
For all benchmark circuits, the method is able to encode all deterministic test patterns using an LFSR whose size is equal to the maximum number of care bits in a test pattern.
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