然而，依照本发明可替换实施例，在数字信号处于逻辑低电平状态时，脉冲也可指时间周期。
However, according to alternative embodiments of the present invention, a pulse can refer to a period of time when a digital signal is in a logic low state.
逻辑信号从高电平到低电平的转换被称为下降沿。
A transition in a logic signal from a logic high to a logic low is referred to as a falling edge.
逻辑信号从高电平到低电平的转换被称为下降沿。
A transition in a logic signal from a logic high to a logic low is referred to as a falling edge.
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