根据这种理论，可以推导得到最优的任意位加法器。
文中给出了用常规的MOS工艺制造二位加法器的设计原理与实验结果。
A 2-word 2-bit adder has been fabricated using conventional MOS technology. Design considerations and experimental results are...
文中给出了用常规的MOS工艺制造二位加法器的设计原理与实验结果。
A 2-word 2-bit adder has been fabricated using conventional MOS technology. Design considerations and experimental results are also given.
在本文中，我们提出8种不同的全加器电路，分别皆使用4位元链波进位加法器将其实现。
We proposed 8 kinds of full adder and all of them are realized in 4 bit ripple carry adder.
设计了4位QSERL串行进位加法器(RCA)电路，和相应的CMOS电路进行了功耗比较。
QSERL 4 bit carry ripple adder (RCA) is designed and compared with static CMOS counterpart.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
文中首先介绍了内建自测试的实现原理，在此基础上以八位行波进位加法器为例，详细介绍了组合电路内建自测试的设计过程。
The BIST of the principle of achieving is introduced first in this paper, then take the 8-bit ripple carry adder as an example, describes the design process of BIST.
使用二进制表示法，在每个26位串行加法器动产位的杠杆转换成一个钟摆在摆动的时钟可见符号。
Using binary notation, 26 movable bit levers inside each bit serial adder convert the swing from the pendulum into a visible notation on the clock.
笔者现已成功地设计了1024位循环式加法器，并应用到RSA密码体系的硬件电路中，得到了较好的效果。
The authors have succeeded in devising a1024bit circular adder and it has been used in the circuit of RSA cryptosystem with a good effect.
提出了一种改进进位运算的32位稀疏树加法器。
A 32-bit sparse tree adder with modified carry tree structure is proposed.
提出了一种改进进位运算的32位稀疏树加法器。
A 32-bit sparse tree adder with modified carry tree structure is proposed.
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