首先介绍了常用并行加法器的设计方法，并在此基础上采用带进位强度的跳跃进位算法，通过逻辑综合和布局布线设计出了一个加法器。
On the basis we design an adder by the adoption of carry skip algorithm with carry strength signals and implement, through logic synthesis and layout.
本文提出了一种能实时完成二进制逻辑运算的光学并行处理系统，并给出了作为半加法器的实验结果。
A real time optical logic processor is presented, that can perform binary logic operations in parallel. Experimental result is given of the system as a half adder.
为了提高加法器的运算速度，提出了一种新型并行整数加法算法——桶形整数加法算法。
To accelerate the adder, a new parallel integer addition algorithm - carry barrel adder algorithm was proposed.
为了提高加法器的运算速度，提出了一种新型并行整数加法算法——桶形整数加法算法。
To accelerate the adder, a new parallel integer addition algorithm - carry barrel adder algorithm was proposed.
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