为了能够在低运算资源的设备上实现鲁棒性前端，在ETSI标准的核心两级维纳滤波算法的基础上，我们提出了一种新方法以提高算法效率。
In order to use the robust feature in low computational resource device, on the basis of two-stage Wiener filtering algorithm in ETSI Standard, we propose a novel approach to improve the efficiency.
浮点加法器是协处理器的核心运算部件，是实现浮点指令各种运算的基础，其设计优化是提高浮点运算速度和精度的关键途径。
High-Speed Floating-point Adder is a critical part in the coprocessor, which is attached to the computing basis of floating-point instructions.
浮点加法器是协处理器的核心运算部件，是实现浮点指令各种运算的基础，其设计优化是提高浮点运算速度和精度的关键途径。
High-Speed Floating-point Adder is a critical part in the coprocessor, which is attached to the computing basis of floating-point instructions.
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