介绍了可编程逻辑控制模块在自动运输线控制系统中的应用，对系统的控制功能及实现方法做了说明，并给出了功能块图。
This paper introduces the application of the universal logic module on automatic conveyor belt control describes and presents the main functions of the system, solutions and soft circuit diagram.
论文根据电能质量谐波监测要求和大规模可编程逻辑器件的特点，设计了一个基于可编程逻辑器件的24位浮点FFT处理模块。
Based on the demand of the power quality 's harmonic monitor and the specialty of large scale programmable logic device, this paper advances a frame of a 24-bit float point FFT module in FPGA.
介绍一种针对正、余弦旋转变压器数字转换器（RDC）模块，用复杂可编程逻辑器件（CPLD）技术实现伺服轴角编码电路设计的方案。
This paper introduces the technology scheme to design radar servo shaft encoder circuit by using CPLD on the rotary transformer and RDC module.
针对煤矿、机场等特殊工业现场，设计了一种基于复杂可编程逻辑器件(CPLD)和光模块的光纤现场总线通讯系统。
A fiber field-bus communication system based on complex programmable logic devices (CPLD) and optical transceiver was designed for some special industrial fields such as colliery and airfields.
主要介绍电气设备中可编程逻辑控制器(plc)、变频器、触摸屏、RS- 485模块及个人电脑之间实现异步通信的软切换。
The soft switching of asynchronous communication among PLC (Programmable Logic Con-troller), transducer, touch screen, RS-485 module and PC is introduced.
本文在此主要通过VHDL语言，利用可编程逻辑器件作为载体来设计usb2.0的协议处理层模块。
This paper mainly talks about designing the protocol layer of USB2.0 with the programmable logical device as the carrier through the VHDL language.
在实际的研制过程中，利用CPLD的在系统可编程（ISP）技术和基于VHDL 语言的可编程逻辑器件设计技术实现了雷达数据采集卡的控制模块。
The control module of the radar data acquisition card is implemented by using of the ISP technology of CPLD and the VHDL programming technology.
分实时和非实时两部分设计一个基于IEC61131 - 3标准的可编程逻辑控制器(plc)梯形图检查模块。
A diagram checking module for PLC base on IEC61131-3 standard is designed and the module is divided into real-time part and non real-time part.
所有的功能模块组合起来后，通过EDA工具进行CPU内核的逻辑综合和功能仿真，最后在可编程逻辑器件上实现这个完整的CPU内核。
CPU core was simulated and synthesized by EDA tools after combine all units. In the end, CPU core was implemented in programmable logic device.
介绍一种基于复杂可编程逻辑器件(CPLD)的通用高性能脉冲幅度分析(PHA)模块设计。
Based on a complicated programmable logical device (CPLD), a miniaturized universal pulse height analysis (PHA) module of high performance is realized.
根据IEC61508对可编程逻辑器件功能安全的要求，提出基于ARM的模拟量输入模块的安全设计。
Aiming at the functional safe demands of programmable electronic systems in IEC61508, this paper proposes the safe design of Analog Input (AI) module based on ARM Microprocessor.
该驱动板以现场可编程逻辑门阵列为DSP与编码器、脉冲命令和功率模块等电路之间的接口，以最新的智能功率模块(IPM)作为功率输出驱动芯片。
FPGA is used as interface between the DSP and the encoder, pulse command and power module. The latest intelligent power module (IPM) is used to provide the function of power stage.
该驱动板以现场可编程逻辑门阵列为DSP与编码器、脉冲命令和功率模块等电路之间的接口，以最新的智能功率模块(IPM)作为功率输出驱动芯片。
FPGA is used as interface between the DSP and the encoder, pulse command and power module. The latest intelligent power module (IPM) is used to provide the function of power stage.
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