在这种模式下，TX信号为高电平期间将重置或空闲。
In this mode, the TX signal will be HIGH during reset or idle.
如果输入信号电平超过可编程阈值，粗调阈值上限指示器就会变为高电平。
If the input signal level exceeds the programmable threshold, the coarse upper threshold indicator goes high.
第一帧(8位)数据发送完毕时，各控制信号均恢复原状态，只有TI保持高电平，呈中断申请状态。
The first frame (8) data sending finished, the control signal are restored the original state, only keep a high level, ti application state interruption.
通常，在数字信号处于逻辑高电平状态时，脉冲指时间周期。
Typically, a pulse refers to a period of time when a digital signal is in a logic high state.
逻辑信号从高电平到低电平的转换被称为下降沿。
A transition in a logic signal from a logic high to a logic low is referred to as a falling edge.
当选择信号为逻辑高电平（1）时，乘法器510传输反相器504的输出信号给发生器404的输出作为输出信号VOUT。
When the select signal is a logic high (1), multiplexer 510 transmits the output signal of inverter 504 to the output of generator 404 as output signal VOUT.
舵机控制程序，舵机的控制信号为周期是20ms的PWM信号，其中高电平持续时间0.5到2。
5ms. -steering control procedure, the servo control signal is 20ms cycle of the PWM signal. margin which lasted 0.5 to 2.5ms.
舵机控制程序，舵机的控制信号为周期是20ms的PWM信号，其中高电平持续时间0.5到2。
5ms. -steering control procedure, the servo control signal is 20ms cycle of the PWM signal. margin which lasted 0.5 to 2.5ms.
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