PPE可以通过在内核模式中使用内存映射寄存器来发起dma传输，而SPE则可以使用在SPU上运行的代码来写入dma通道。
The ppe does this through memory-mapped register access from kernel mode, while the SPE writes to its DMA channels from code running on the SPU.
mftb指令可以将tb寄存器的值传输到一个通用寄存器中。
The MFTB mnemonic allows the value of the TB register to be transferred to a general purpose register. Its syntax is.
寄存器传输级(rtl)综合实现从rtl行为描述到门级结构描述的转换，是目前EDA设计行业的主流设计方法。
As the behavior of digital system can be fully described by the register transfer level (RTL) behavior descriptor, so RTL synthesis has become the mainstream design method in EDA domain.
高层次综合也叫行为级综合，其基本任务是完成数字系统行为描述到寄存器传输级（RTL）描述的转换。
The main task is translating the behavioral description of a digital system into the design of RTL(Register Transfer Level).
由于寄存器传输级(rtl)行为描述可以精确地确定数字系统的操作，所以寄存器传输级综合成为当前EDA行业的主流设计方法。
Because the behaviors of digital system can be described by register transfer level (RTL) behavior exactly, RTL synthesis becomes the mainstream design method in EDA domain.
寄存器传输级（RTL）描述是目前应用最广泛的电路设计描述形式。
The Register Transfer Level (RTL) behavioral descriptions are widely used in IC designs.
验证是当前越来越复杂的集成电路设计中的瓶颈，在寄存器传输级（RTL）直接做验证是目前比较有效的一种途径。
Verification is the bottleneck of more and more complex integrated circuit designs, and doing verification directly on register transfer level (RTL) is a promising solution.
通过对SCSI控制器相关寄存器的设置和SCSI协议扩展消息的交互，实现了主机存储通道的数据传输速度达到160MB/s。
The speed of data transfer between SCSI devices is upto 160MB/s implemented by the setting of registers in the SCSI controller and the intercourse of expended SCSI protocol messages.
该数据选通器主要由CMOS传输门和CMOS移位寄存器构成，能同时适用于数字信号与模拟信号。
This device is constituted by CMOS transmission and CMOS shift register and is able to apply to the digital signal and analog signal at the same time.
此外，还用QUARTURSII软件对仿真控制逻辑进行了寄存器传输级的仿真与验证。
In addition, we verified and emulated the emulating logic by Register Transfer Language. Last of all, we presented the test program and circuit with QUARTURSII.
该实例是利用AT 90CAN 128这块芯片做主控芯片，ATA6660做CAN的控制器，通过对芯片里面的寄存器进行操控，来完成对数据的传输。
The instance utilizes the chip AT90CAN128 as the main chip and the chip ATA6660 as Can transceiver. The Can bus transmits the data by controlling the inside registers.
集成电路设计在寄存器传输级的设计方法已经非常成熟。
实现PCI9054与计算机PCI总线的接口，包括总线仲裁，寄存器读写操作，EEPROM的配置和下载，DMA传输，中断响应等功能。
Realize the interface between PCI9054 and the PCI bus, including the bus arbitration, read and write of the registers, the configuration of the EEPROM, the DMA transfer, interrupt response and so on.
还有一些人会说esl是优于寄存器传输级(rtl)的更高的抽象层次。
Still others would say that ESL refers to anything that's at a higher level of abstraction than register transfer level (RTL) representations.
本文主要是对大规模、超大规模集成电路寄存器传输级（RTL）的自动测试产生算法进行研究。
This dissertation focuses on automatic test generation (ATPG) algorithms for very large-scale integrated circuits at register-transfer-level (RTL).
上述工作是为了建立一个将寄存器传输级语言描述翻译成硬件逻辑图的自动逻辑综合系统。
The above work is intended to set up an automatic logic synthesis system to translate a register transfer level language descriptions into hardware logic diagrams.
第五章设计了全p沟道tft构成的屏上驱动电路，包括反相器、移位寄存器、传输门的设计，并用仿真软件进行了仿真验证。
In chapter 5, the on-screen driving circuits composed of P-channel TFT have been designed, including inverter, shift register, transmission gate and simulated using simulation software.
本设计采用模块化设计的思想，将GPIB接口IP核分成三个模块：GPIB接口功能模块、内部寄存器模块和数据传输控制模块。
Based on the theory of modularization, the IP core of GPIB is divided into three modules: module for port function of GPIB, module for inner register and module for data transmission.
文章讨论了寄存器传输级结构对综合方法的影响，并提出使用分模块的寄存器传输级结构作为高层次综合的目标结构。
The influence of architectures on synthesis methods is discussed, and a clustered register transfer level architecture as object architecture is presented.
利用传输门实现了32位桶式移位寄存器，其具体功能包括算术右移，逻辑左移，逻辑右移和循环右移。
In this paper, we realized Barrel Shifter of 32 bits by using transpost gates, its functions including arithmetic shift right, logic shift left, logic shift right and rotate right.
第四章在FPGA平台上实现载波同步单元电路，并给出了实现后的FPGA资源消耗、寄存器传输逻辑(rtl)原理图。
In chapter 4, the circuit of the carrier synchronization unit is implemented on FPGA, the Resistor Transistor Logic (RTL) schemes are presented.
第四章在FPGA平台上实现载波同步单元电路，并给出了实现后的FPGA资源消耗、寄存器传输逻辑(rtl)原理图。
In chapter 4, the circuit of the carrier synchronization unit is implemented on FPGA, the Resistor Transistor Logic (RTL) schemes are presented.
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